This invention relates to supervisory circuits for the measurement of low frequency signals and control of power supplies.
Electrical measurement metering in power management has been traditionally carried out by analog devices while the electronics industry has been basically converted from analog devices to digital devices primarily computers and other electronic digital apparatus. In keeping with the development of the electronic field it is important that electronic devices such as power management devices be reduced to very small size but still maintain increased flexibility to improve turnaround time in manufacturing so that a basic circuit design can be used in many different devices with only minor modification or reprogramming at the most to fulfill the new function or provide the new voltage or power levels desired.
The need for reliable power supplies has become increasingly important as circuit densities and hence functionality of the various systems powered by these power supplies continue to rise. Unforeseen failure of power supplies in a computer system, for example would be catastrophic, as it can result in the loss of valuable data. As a result, constant supervision or monitoring of the power supply is required and this has made it necessary to include specialized power supervisory circuits within such systems. These supervisory circuits keep the over all system informed about the integrity of the power supply and hence allows for the safe shutdown of the dependent systems in case this integrity is breached.
Generally, supervisory circuits monitor the voltage or current levels of analog voltages or currents and inform the system on whether the signals are within the allowed range of operation. The operating range is fairly large (typically +/xe2x88x9210% of a pre-specified value) and hence, the resolution required to monitor the signal is not too demanding with a +/xe2x88x922% full-scale resolution being sufficient. Furthermore, the monitored signals have low bandwidths since they are usually the dc output voltage (current) or ac-line input voltage (current) of the power supply. A supervisory circuit, however, may be required to monitor a number of signals simultaneously as a mixed analog-digital system may operate off a number of different voltage levels. Existing power-supervisory applications specific integrated circuits (PS-ASIC) are primarily analog in nature and function sufficiently well in this context. These PS-ASICs, however, are found to be inflexible to changes in component tolerance values that occur during the manufacturing process and are fixed in their signal processing operations once they are set into the product. It would be advantageous therefore to have a PS-ASIC that would accommodate drifts in threshold values due to aging, product upgrades during the lifetime of a product, and alteration of the signal processing capabilities of the PS-ASIC.
Such a PS-ASIC would be xe2x80x9creconfigurablexe2x80x9d or field upgradeable and also make possible the use of a single PS-ASIC in a wide range of similar products thereby reducing development costs and time to market.
Until recently, analog based circuit techniques were used for signal processing. These circuits were implemented in bipolar technology and required the use of accurate voltage and current sources as well as precision resistor divider networks for every parametric threshold detection routine used. This was area intensive and due to the drifts that occurred in the references it was also found to be prone to failure in terms of meeting operating specifications. Furthermore, the advent of switched-mode power supplies introduced the ASIC to noisier operating environments making it even more prone to false threshold detection problems. Masking times for threshold faults were achieved by the use of external components (to set RC time constants) which made the PS-ASIC once again susceptible to component tolerance problems. As far as more complex computation were concerned, they all basically relied on obtaining the average time that a waveform (such as the ac line voltage) exceeded a certain threshold value before the resulting average would trip a parametric test. Hence, the computational complexity of these circuits was limited. Finally, the ASIC was fixed in terms of its application to a specific product and hence was not flexible to operate on updated specifications on the same product or other products. These problems have thus made the use of present implementation techniques unattractive.
Switched capacitor circuit techniques make it possible to design programmable mixed analog-digital circuits. For example, a xe2x80x9cprogrammable capacitor arrayxe2x80x9d (PCA) used in an amplifier feedback can result in programmable gains that are controlled by digital co-efficients. PCA""s can be used in comparator circuits to obtain programmable trip points by distributing the charge in the PCA to attain the desired threshold voltage. This technique can give a fair degree of programmability in terms of some basic signal processing. However, using PCAs as the primary implementation technique can be expensive in terms of an ASIC layout. For example, an eight bit resolution would require a capacitance spread, (Cmax/Cmin) of 256. Since very small capacitors are undesirable due to increased noise (kT/C noise) and mask resolution inaccuracies and in addition need to be at least an order of magnitude greater than the parasitic capacitance within the circuit (the gate-to-source capacitance of a minimum size CMOS transistor in a typical 1.2 micro-meters CMOS process is 20 Femtoferads (fF)) one is limited in the maximum value of capacitance chosen. For a Cmin of 200 fF, a Cmax/Cmin of 256 would give a Cmax of 51 pF. Given that in a typical 1.2 micro-meter CMOS process, 1 pF occupies approximately 1290 micro-meter2 this makes Cmax alone occupy 66,000 micro-meters2 (approximately 102 mil2). One can see that area requirements may become quite demanding for an implementation that requires a number of such switched capacitor configurations.
U.S. Pat. No. 5,345,409 makes use of digital signal processors (DSPs) and is incorporated herein by reference. Digital signal processors have gained widespread use in a number of applications including power monitoring as can be seen by the above reference. They are capable of computationally intensive tasks and are programmable by software. The reference discloses a programmable power metering ASIC comprised of a mixed analog-digital circuit that uses a customized DSP for computations. Six Delta-Sigma analog to digital converters are used to provide an oversampled serial bit-stream of information from the six source signals (three in voltage mode and three in current mode). This information is low pass filtered and decimated using digital filtering techniques. The resulting output is fed to the DSP which has two programmable processors that are used to execute calibration and computing operations using the algorithms stored in and off-chip PROM. This allows the ASIC to compute the RMS values, real and apparent power consumptions and power factor rating of the source signals. The final readings are measured to give an absolute accuracy of 0.04% when using the calibration coefficients. The performance of this implementation comes at the expense of silicon die area. The ASIC corresponding to the structure disclosed in the reference occupies about 6.4 mmxc3x977.1 mm in 1.5 micro-meter CMOS technology (most of which is occupied by the DSP) in order to monitor six signals.
One of the objectives of the present invention is to provide sufficient signal processing capability while minimizing the amount of silicon die area required in order to reduce cost and still provide the necessary function.
The invention described herein provides a moderately accurate (less than 2% full-scale error) programmabe supervisory circuit that can monitor a number of critical low frequency signals in a complex power supply by applying stochastic and pulse density based computational techniques.
Stochastic computing techniques were developed in the mid-sixties in an effort to obtain parallel computing structures for neural networks. Stochastic computing relies on principles based on Boolean algebra and probabilistic mathematics. Analog quantities are represented in terms of a probabilistic digital bit-stream and the resulting hardware needed for signal processing becomes very simple in comparison to that required by conventional digital or analog methodologies. This hardware simplicity comes at the expense of computational accuracy but the desired operating specification for a supervisory circuit can still be easily met. Furthermore, the implementation in digital circuitry gives it an advantage over analog implementations since it means better noise immunity (important in switch mode power supplies) and easier testability. Most importantly, it also allows the circuit to be reconfigurable when field-programmable gate array technology is used. The encoding of the analog signal can be done by using Delta-Sigma Modulation (DSM) to obtain a highly oversampled serial pulse density modulated digital bit-stream. This encoded representation of the analog signal can then be processed by a stochastic computer. Delta-Sigma modulation can be used to simplify digital filter structures by providing an alternative way to multiply digital filter coefficients in a filter. This is used to advantage in one aspect of the invention in order to implement one aspect of the supervisory function.
The invention herein provides a power supervisory circuit and attendant applications which together provide simplicity, robustness and programmability with the integration of stochastic and DSM based computations to perform threshold, means squared and RMS outputs which can be used to control power supplies or for monitoring purposes.
The invention herein provides a supervisory circuit which is adapted to monitor an input signal and produce as an output signal, a parametric signal corresponding to the input signal. The circuit includes an input for receiving the input signal, and a stochastic processor coupled to the input for receiving the input signal and processing it to derive a signal that represents a parametric measure of the input signal. An output connected to said stochastic processor provides the parametric output signal as an output for supervisory purposes.
Typically the input signal is an analog voltage and the stochastic processor is adapted to produce an output voltage signal which is proportional to the RMS value of the voltage of the input signal.
The supervisory circuit may preferably comprise an input for receiving the input signal, a mean square processor for determining the mean square value of the input voltage; a conversion processor for converting the mean square value into a random pulse density modulated bitstream representative of the mean square value; a stochastic processor conversion processor for converting the random pulse density modulated bitstream into a stochastic representation of the RMS value of the input voltage, and an output for outputting the stochastic representation of the RMS value.
An embodiment of the supervisory circuit for deriving a parametric output signal of an analog input signal may comprise an input delta-sigma analog to digital converter adapted to produce a serial pulse density modulated bit stream representation of the analog input signal, a running averager processor adapted to process the bit stream representation of the analog input signal to produce a representation of the running average of the bitstream; a multi bit modulated squarer processor adapted to calculate the square of the running average and integrate the square over a suitable time period to derive a parallel binary representation of the mean square value of the analog input signal; a randomizer adapted to convert the binary representation of the mean square value of the analog input signal to a serial random pulse density modulated bitstream; a stochastic square root processor adapted to process the random pulse density modulated bitstream to produce a parametric signal corresponding the root mean square value of the analog input signal; and, output means to output said root mean square value signal.
In another embodiment the stochastic square root processor is adapted to accept the serial random pulse density modulated bitstream as input and uses as negative feedback the stochastic square of the output of the stochastic processor to produce an output corresponding to the root mean square value of the analog input signal.
The running averager processor may be adapted to process the serial bit stream representation of the analog input signal to produce a parallel representation of the running average of the bitstream.
Preferably, the multi bit modulated squarer processor is adapted to calculate the square of the running average by modulating the average by the serial pulse density modulated bitstream representation of the analog input signal to obtain a multi bit representation of the analog input signal squared, and integrate the square over the period of the input signal or a suitable timer period to derive a parallel binary representation of the mean square value of the analog input signal.
The stochastic square root processor may include:
a) an up down counter having incrementing and decrementing inputs, and an output, and being adapted to receive the random pulse density modulated bitstream at the incrementing input, the output signal of the counter being converted by a randomizer to an output random pulse density modulated bitstream,
b) a feedback circuit, the output bitstream being further modified by the feedback circuit to provide a decrementing input to the counter, the feedback circuit comprising:
i) a decorrelator to decorrelate the output bitstream; and,
ii) means to feed back the boolean product of the output bitstream and the decorrelated bitstream (obtaining a squared representation of output value of the counter) to the decrementing input of the counter,
the output signal of the counter representing the square root of the mean square input, thereby producing a parametric signal which corresponds to the root mean square value of the analog input signal.
The supervisory circuit may further include a threshold status apparatus adapted to respond to a signal derived by a processor of the supervisory circuit to produce a threshold status output when the signal is within a preselected range of values. The threshold status apparatus may preferably be adapted to respond to the signal when the signal is within any of acceptable, unacceptable, or marginal range of conditions.
The threshold status apparatus may be adapted to respond to the root mean square value output of the supervisory circuit, or the output signal of any of the processors of the supervisory circuit may be made available externally.
Another aspect of the invention provides a power supply which includes a power convertor for converting an input into a regulated output, and a supervisory circuit for supervising the power convertor. The power convertor is governed by the supervisory circuit, the supervisory circuit providing an output control signal to the power convertor which is derived from stochastic processing of an analog input signal corresponding to the input to the power supply.